Semiconductor memory device

ABSTRACT

A semiconductor memory device including different types of memories capable of attaining further miniaturization (thinning) and speed-up. This semiconductor memory device comprises a first memory including a bit line, a word line arranged to intersect with the bit line and storage means ( 43 ) arranged between the bit line and the word line and a second memory ( 13 ) different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate ( 31 ). When forming the first memory and the second memory on the same semiconductor substrate ( 31 ) in a stacked manner in this case, the thickness in the height direction is reduced, whereby further miniaturization (thinning) can be attained. Further, no wire having a large parasitic capacitance or solder may be employed for connection of the first memory and the second memory, whereby high-speed data transfer is enabled between the first memory and the second memory.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory device,and more specifically, it relates to a semiconductor memory deviceincluding different types of memories.

BACKGROUND TECHNIQUE

[0002] In general, a portable device adopting computer architectureemploys an SRAM (Static Random Access Memory) exhibiting a high speed asa main storage part while a highly integrated nonvolatile flash memoryis used as an auxiliary storage part. FIG. 21 is a block diagram showingthe structure of a memory system in a conventional portable devicehaving such a structure. In the prior art shown in FIG. 21, an SRAM 102is employed as a main storage part storing data of a CPU (centralprocessing unit) 103. A flash memory 101 is employed as an auxiliarystorage part.

[0003] In the case of the conventional structure shown in FIG. 21, twochips of the flash memory 101 and the SRAM 102 are generally required,and hence this is disadvantageous to miniaturization of the device. Thisstructure is also disadvantageous in speed since a delay is caused bywires between the chips.

[0004] In order to solve such inconvenience, a product prepared bypasting a chip of a flash memory 101 and a chip of an SRAM 102 togetherand storing the same in a single package has also been developed inrecent years. FIG. 22 is a perspective view showing the structure ofsuch a conventionally developed semiconductor package. In thissemiconductor package, it is possible to deal with a certain degree ofminiaturization by superposing the chip of the flash memory 101 and thechip of the SRAM 102 vertically, as shown in FIG. 22.

[0005] In the product shown in FIG. 22 prepared by superposing the chipof the flash memory 101 and the chip of the SRAM 102 vertically andstoring the same in the single package, however, it has been difficultto reduce the thickness in the height direction due to the superpositionof the two chips. Thus, there has been such a problem that it isdifficult to attain further miniaturization (thinning).

[0006] Further, the chip of the flash memory 101 and the chip of theSRAM 102 are wired with wires 104 by solder or the like, and henceparasitic capacitances increase. Thus, there has also been such aproblem that power consumption enlarges to inhibit speed-up.

[0007] With respect to requirement for reduction of the power supplyvoltage for the portable device, there has been such inconvenience thata high voltage is required for writing in memory cells of the flashmemory 101. There has also been such inconvenience that the area andpower consumption of a step-up circuit 101 a for generating a highvoltage enlarge. Therefore, it has been difficult to attain reduction ofthe power supply voltage and reduction of power consumption of theportable device.

[0008] A ferroelectric memory is known as one of recently remarkednonvolatile memories. This ferroelectric memory is a memory utilizingcapacitance change responsive to the direction of polarization of aferroelectric substance as a memory element. This ferroelectric memory,capable of data writing at a high speed and a low voltage in principle,is remarked as a nonvolatile memory of the next generation.

[0009] Among memory cell systems for the ferroelectric memory, atwo-transistor two-capacitor system and a one-transistor one-capacitorsystem are lower in degree of integration as compared with the flashmemory, and hence insufficient as substitutions for the flash memory. Onthe other hand, a simple matrix ferroelectric memory has a simplestructure of merely arranging ferroelectric capacitors on theintersections between word lines and bit lines can be highly integrated.Therefore, the simple matrix ferroelectric memory is remarked as asubstitutable memory for the flash memory.

[0010] However, the simple matrix ferroelectric memory has a problem ofsuch disturbance that data in non-selected cells disappear. In otherwords, it follows that a voltage of ½Vcc is applied to non-selectedmemory cells connected to a selected bit line and a selected word linein writing and reading. Therefore, there is such a problem that thequantity of polarization gradually decreases due to hystereticproperties of the ferroelectric substance and the data disappear as aresult.

DISCLOSURE OF THE INVENTION

[0011] An object of the present invention is to provide a semiconductormemory device capable of attaining further miniaturization (thinning)and speed-up in the case of including different types of memories.

[0012] Another object of the present invention is to prevent disturbancein the aforementioned semiconductor memory device.

[0013] Still another object of the present invention is to attainreduction of a voltage and reduction of power consumption in theaforementioned semiconductor memory device.

[0014] A semiconductor memory device according to a first aspect of thepresent invention comprises a first memory including a bit line, a wordline arranged to intersect with the bit line and storage means arrangedbetween the bit line and the word line and a second memory different intype from the first memory. The first memory and the second memory areformed on a semiconductor substrate.

[0015] In this semiconductor memory device according to the firstaspect, as hereinabove described, the first memory and the second memoryare so formed on the semiconductor substrate that it is possible toreduce the thickness in the height direction when forming the firstmemory and the second memory on the identical semiconductor substrate ina stacked manner, for example, whereby further miniaturization(thinning) can be attained. When forming the first memory and the secondmemory on the semiconductor substrate in a stacked manner, further, nowire having a large parasitic capacitance or solder may be employed forconnection of the first memory and the second memory but the memoriescan be closely arranged, whereby high-speed data transfer is enabledbetween the first memory and the second memory.

[0016] In the aforementioned semiconductor memory according to the firstaspect, the first memory and the second memory are preferably formed onthe identical semiconductor substrate in a stacked manner.

[0017] In the aforementioned semiconductor memory device according tothe first aspect, at least either the word line or the bit line ispreferably shared by the first memory and the second memory. Accordingto this structure, the number of the bit line and the word line can bereduced, whereby the structure can be simplified.

[0018] In the aforementioned semiconductor memory device according tothe first aspect, the first memory preferably includes a plurality ofmemory cell arrays each including a plurality of memory cells, the bitline preferably includes a main bit line and an auxiliary bit lineconnected to the main bit line and arranged every memory cell array, theword line preferably includes a main word line and an auxiliary wordline connected to the main word line and arranged every memory cellarray, and the memory cells of the first memory are preferably connectedto the auxiliary word line and the auxiliary bit line. Thus, the bitlines and the word lines are so brought into a hierarchical structurethat wires connected to the memory cells shorten, whereby wiringcapacitances decrease. Thus, high-speed reading can be performed.

[0019] In this case, the first memory preferably includes aferroelectric memory, and the memory cells of the ferroelectric memorypreferably include the auxiliary bit line, the auxiliary word line and aferroelectric layer serving as the storage means arranged between theauxiliary bit line and the auxiliary word line. According to thisstructure, a first memory consisting of a simple matrix ferroelectricmemory can be easily implemented. In this case, the second memorypreferably includes a static memory, and the main bit line is preferablyshared by the ferroelectric memory constituting the first memory and thestatic memory constituting the second memory. According to thisstructure, the structure can be simplified as compared with a case ofseparately providing main bit lines respectively.

[0020] In the aforementioned structure having the bit lines and the wordlines of the hierarchical structure, the main bit line and the auxiliarybit line are preferably formed on the identical semiconductor substratein a stacked manner, and the main word line and the auxiliary word lineare preferably formed on the identical semiconductor substrate in astacked manner. According to this structure, the hierarchical structureof the bit lines and the word lines can be easily formed. In this case,the main bit line and the main word line may be formed above theauxiliary bit line and the auxiliary word line.

[0021] In the aforementioned structure having the bit lines and the wordlines of the hierarchical structure, the semiconductor memory devicepreferably further comprises a first selector transistor connectedbetween the auxiliary bit line and the main bit line and a secondselector transistor connected between the auxiliary word line and themain word line. According to this structure, a prescribed auxiliary wordline and a prescribed auxiliary bit line can be selected through thefirst selector transistor and the second selector transistor, whereby aprescribed memory cell of the first memory can be easily selected forperforming data writing and reading. In this case, the semiconductormemory device preferably further comprises a first selection lineconnected to the gate of the first selector transistor and a secondselection line connected to the gate of the second selector transistor.According to this structure, the first selector transistor and thesecond selector transistor can be easily turned on/off through the firstselection line and the second selection line.

[0022] In the aforementioned structure having the bit lines and the wordlines of the hierarchical structure, the second memory is preferablyconnected to the main bit line and provided every memory cell array.According to this structure, it is possible to make the second memoryarranged every memory cell array function as a high-speed cache memory.

[0023] In the aforementioned structure having the bit lines and the wordlines of the hierarchical structure, the semiconductor memory devicepreferably further comprises a transistor connected between the secondmemory and the main bit line. According to this structure, the secondmemory of a selected memory cell array and the main bit line can beconnected with each other through this transistor. In this case, thesemiconductor memory device preferably further comprises a thirdselection line connected to the gate of the transistor connected betweenthe second memory and the main bit line. According to this structure,the transistor connected between the second memory and the main bit linecan be easily turned on/off through the third selection line.

[0024] In the aforementioned semiconductor memory device according tothe first aspect, the first memory preferably includes a ferroelectricmemory, the second memory preferably includes a static memory, and theferroelectric memory is preferably formed above the static memory in astacked manner. According to this structure, it is possible to implementa memory system consisting of a ferroelectric memory and a static memorycapable of attaining further miniaturization (thinning) and speed-up.Further, the ferroelectric memory requires no high voltage in writingdissimilarly to a flash memory, whereby it is possible to attainreduction of the voltage and reduction of power consumption.

[0025] In the aforementioned semiconductor memory device according tothe first aspect, the first memory preferably includes a magneticmemory, the second memory preferably includes a static memory, and themagnetic memory is preferably formed above the static memory in astacked manner. According to this structure, it is possible to implementa memory system consisting of a magnetic memory and a static memorycapable of attaining further miniaturization (thinning) and speed-up.

[0026] In the aforementioned semiconductor memory device according tothe first aspect, the said first memory preferably includes a phasechange memory, the second memory preferably includes a static memory,and the phase change memory is preferably formed above the static memoryin a stacked manner. According to this structure, it is possible toimplement a memory system consisting of a phase change memory and astatic memory capable of attaining further miniaturization (thinning)and speed-up.

[0027] In the aforementioned semiconductor memory device according tothe first aspect, the said first memory preferably includes an anti-fuseROM, the second memory preferably includes a static memory, and theanti-fuse ROM is preferably formed above the static memory in a stackedmanner. According to this structure, it is possible to implement amemory system consisting of an anti-fuse ROM and a static memory capableof attaining further miniaturization (thinning) and speed-up.

[0028] In the aforementioned structure having the bit lines and the wordlines of the hierarchical structure, the semiconductor memory devicepreferably further comprises frequency detection means arranged everymemory cell array for detecting a write frequency and a read frequencyof the memory cells of the first memory included in each memory cellarray and refresh means performing rewriting with respect to the memorycells of the first memory included in the memory cell array on the basisof that the sum of the write frequency and the read frequency detectedby the frequency detection means has reached a prescribed frequency.According to this structure, a refresh operation can be so periodicallyperformed that it is possible to prevent such disturbance that data ofnon-selected cells of the first memory disappear. Further, the frequencydetection means is so provided every memory cell array that the refreshoperation can be performed every memory cell array, whereby it ispossible to reduce the frequency of disturbance applied to the memorycells in refreshing as compared with a case of performing the refresh(rewrite) operation on all memory cells. Thus, no data disappears due tothe refresh (rewrite) operation. In this case, the frequency detectionmeans may include a counter.

[0029] In the aforementioned structure having the frequency detectionmeans, the first memory are preferably formed on the semiconductorsubstrate in a stacked manner. According to this structure, it ispossible to attain further miniaturization (thinning).

[0030] In the aforementioned semiconductor memory device according tothe first aspect, the second memory is provided at the rate of one tothe plurality of memory cells of the first memory. According to thisstructure, it is possible to further reduce influence exerted by thesecond memory on the degree of integration of the memory cells of thefirst memory as compared with a case of providing the second memoryevery memory cell of the first memory.

[0031] A semiconductor memory device according to a second aspect of thepresent invention comprises a nonvolatile first memory including memorycells arranged in the form of a matrix and a volatile second memory. Thefirst memory and the second memory are formed on the identicalsemiconductor substrate in a stacked manner.

[0032] In this second semiconductor memory device according to thesecond aspect, as hereinabove described, the nonvolatile first memoryand the volatile second memory are so formed on the identicalsemiconductor substrate in a stacked manner that the thickness in theheight direction can be reduced, whereby it is possible to attainfurther miniaturization (thinning). Further, the first memory and thesecond memory are so formed on the semiconductor substrate in a stackedmemory that no wire having a large parasitic capacitance or solder maybe employed for connection of the first memory and the second memory butthe memories can be closely arranged, whereby high-speed data transferis enabled between the first memory and the second memory.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a plan view showing the overall structure of asemiconductor memory device according to a first embodiment of thepresent invention.

[0034]FIG. 2 is a model diagram conceptually showing the structure of amemory cell array part in the semiconductor memory device according tothe first embodiment shown in FIG. 1.

[0035]FIG. 3 is an equivalent circuit diagram showing a first selectortransistor in the semiconductor memory device according to the firstembodiment shown in FIG. 2.

[0036]FIG. 4 is an equivalent circuit diagram showing a second selectortransistor in the semiconductor memory device according to the firstembodiment shown in FIG. 2.

[0037]FIG. 5 is an equivalent circuit diagram showing the structure ofan SRAM part in the semiconductor memory device according to the firstembodiment shown in FIG. 2.

[0038]FIG. 6 is a block diagram showing the overall structure of aferroelectric memory in the semiconductor memory device according to thefirst embodiment shown in FIG. 2.

[0039]FIG. 7 is a plane layout diagram showing the overall structure ofthe semiconductor memory device according to the first embodiment of thepresent invention.

[0040]FIG. 8 is a sectional view of the semiconductor memory deviceaccording to the first embodiment shown in FIG. 7 taken along the line200-200.

[0041]FIG. 9 is a plane layout diagram of the SRAM part of thesemiconductor memory device according to the first embodiment of thepresent invention.

[0042]FIG. 10 is a circuit diagram corresponding to the plane layoutdiagram shown in FIG. 9.

[0043]FIG. 11 is a plane layout diagram of the memory cell part of thesemiconductor memory device according to the first embodiment of thepresent invention.

[0044]FIG. 12 is a plane layout diagram of a global word line and globalbit line part of the semiconductor memory device according to the firstembodiment of the present invention.

[0045]FIG. 13 is a perspective view for illustrating the structure of acounter part of a semiconductor memory device according to a secondembodiment of the present invention.

[0046]FIG. 14 is an equivalent circuit diagram showing the internalstructure of the counter part according to the second embodiment shownin FIG. 13.

[0047]FIG. 15 is a plane layout diagram of the semiconductor memorydevice according to the second embodiment of the present invention.

[0048]FIG. 16 is a sectional view of the semiconductor memory deviceaccording to the second embodiment shown in FIG. 15 taken along the line300-300.

[0049]FIG. 17 is a plane layout diagram of the counter part of thesemiconductor memory device according to the second embodiment of thepresent invention.

[0050]FIG. 18 is a perspective view showing a semiconductor memorydevice according to a modification of the first or second embodiment ofthe present invention.

[0051]FIG. 19 is a perspective view for illustrating a fabricationprocess for the semiconductor memory device according to themodification shown in FIG. 18.

[0052]FIG. 20 is a perspective view for illustrating the fabricationprocess for the semiconductor memory device according to themodification shown in FIG. 18.

[0053]FIG. 21 is a block diagram showing the structure of a conventionalmemory system including an SRAM and a flash memory.

[0054]FIG. 22 is a perspective view showing the structure of aconventional semiconductor package including an SRAM chip and a flashmemory chip.

BEST MODES FOR CARRYING OUT THE INVENTION

[0055] Embodiments of the present invention are now described withreference to the drawings.

[0056] First Embodiment

[0057] As shown in FIGS. 1 and 2, 4×4=16 memory cells 10 of anonvolatile ferroelectric memory (FeRAM) and 4-bit volatile SRAMs 13 arearranged on each of memory cell arrays 1 a, 1 b, 1 c and 1 d in asemiconductor memory device according to this first embodiment. Thememory cells 10 of the ferroelectric memory are connected to local wordlines LWL and local bit lines LBL. The local bit lines LBL are connectedto global bit lines GBL through first selector transistors 11. The localword lines LWL are connected to global word lines GWL through secondselector transistors 12.

[0058] The ferroelectric memory is an example of the “first memory” inthe present invention, and the SRAMs 13 are examples of the “secondmemory” or the “static memory” in the present invention. The global wordlines GWL are examples of the “main word line” in the present invention,and the local word lines LWL are examples of the “auxiliary word line”in the present invention. The global bit lines GBL are examples of the“main bit line” in the present invention, and the local bit lines LBLare examples of the “auxiliary word line” in the present invention.

[0059] The first selector transistors 11 are turned on/off through RAAlines (row array selection address lines). The second selectortransistors 12 are turned on/off through CAA lines (column arrayselection address lines). The RAA lines are examples of the “firstselection line” in the present invention, and the CAA lines are examplesof the “second selection line” in the present invention.

[0060] Each first selector transistor 11 is constituted of an n-channelMOS transistor as shown in FIG. 3, and each second selector transistor12 is constituted of an n-channel transistor as shown in FIG. 4. EachRAA line is connected to the gate of the first selector transistor 11,and each CAA line is connected to the gate of the second selectortransistor 12. Each SRAM 13 is constituted of two inverter circuits, asshown in FIG. 5. The SRAM 13 is connected to each global bit line GBLthrough a transistor 14, while each RAAS line is connected to the gateof the transistor 14. The RAAS line is an example of the “thirdselection line” in the present invention.

[0061] According to this first embodiment, the global bit lines GBL areshared by the ferroelectric memory and the SRAMs 13.

[0062] The ferroelectric memory shown in FIG. 2 comprises a plurality ofmemory cell arrays 1 a, 1 b, . . . 1 n, a row decoder 2, a columndecoder 3, a row address buffer 4, a column address buffer 5, aread/write amplifier 6 and a control part (clock generation part) 7, asshown in FIG. 6.

[0063] The plane layout of the semiconductor memory device according tothe first embodiment shown in FIG. 2 and a sectional structurecorresponding thereto are now described with reference to FIGS. 7 to 12.

[0064] In the semiconductor memory device according to the firstembodiment, the second selector transistors 12 each consisting of a pairof n-type source/drain regions 32 and a gate electrode 33 are formed onthe surface of a p-type semiconductor substrate 31, as shown in FIGS. 7and 8. Each CAA line 46 is connected to the gate electrode 33 of thesecond selector transistor 12. Two n-channel transistors consisting ofn-type source/drain regions 38 and gate electrodes 39 are formed on thesurface of the p-type semiconductor substrate 31. Each SRAM 13 is formedby these two n-channel transistors and two p-channel transistors notillustrated in the section of FIG. 8 (see FIG. 10).

[0065] Wiring layers 40 are connected to the n-type source/drain regions38 on both ends of the n-channel transistors constituting the SRAM 13,while a GND line 41 b is connected to the central n-type source/drainregion 38.

[0066] A local word line (LWL) 44 is connected to one n-typesource/drain region 32 of the second selector transistor 12. Local bitlines (LBL) 42 are formed on the lower surface of the local word line(LWL) 44 through ferroelectric layers 43. The simple matrix memory cells10 consisting of ferroelectric capacitors are constituted of these localbit lines (LBL) 42, the ferroelectric layers 43 and the local word line(LWL) 44. The ferroelectric layers are examples of the “storage means”in the present invention.

[0067] A global word line (GWL) 45 is formed to be connected to theother n-type source/drain region 32 of the second selector transistor 12while extending above the local word line (LWL) 44. Global bit lines(GBL) 47 are formed above the global word line (GWL) 45 to correspond tothe local bit lines (LBL) 42.

[0068] In the plane layout diagram shown in FIG. 7 and the sectionalstructure shown in FIG. 8, the global word lines GWL and the global bitlines GBL are formed above the local word lines LWL and the local bitlines LBL, dissimilarly to the model diagram shown in FIG. 2. Thus, whenit is intended to implement the hierarchical structure of the local wordlines LWL and the local bit lines LBL as well as the global word linesGWL and the global bit lines GBL of the model diagram shown in FIG. 2 inpractice, this results in the structure shown in FIGS. 7 and 8.

[0069] As the plane layout of an SRAM part, the wiring layers 40 areformed by first wiring layers while Vcc lines 41 a and GND lines 41 bare formed by second wiring layers, as shown in FIG. 9. Further, theSRAM part includes two p-channel transistors and two n-channeltransistors, as shown in FIG. 10.

[0070] As the plane layout of a memory cell part, the local bit lines(LBL) 42 are formed by third wiring layers while the local word lines(LWL) 44 are formed by fourth wiring layers, as shown in FIG. 11. Theferroelectric layers 43 are arranged on the intersections between thelocal bit lines (LBL) 42 and the local word lines (LWL) 44.

[0071] As the plane layout of a global word line (GWL) and global bitline (GBL) part, the global word lines (GWL) 45 are formed by fifthwiring layers while the global bit lines (GBL) 47 and the CAA lines 46are formed by sixth wiring layers, as shown in FIG. 12.

[0072] The outline of operations of the semiconductor memory deviceaccording to the first embodiment constituted as described above is nowdescribed. A case of accessing four memory cells 10 of the ferroelectricmemory connected to a local word line LWL2 in an array (n,m) shown inFIG. 2 is assumed here. In this case, the selected array is the array(n,m), whereby a CAAm line and an RAAn line are so activated that thearray is first selected. Both of the first selector transistors 11 andthe second selector transistors 12 enter ON states due to thisactivation of the CAAm line and the RAAn line, whereby local word linesLWL1 to 4 are connected to global word lines GWLn1 to n4 respectivelywhile local bit lines LBL1 to 4 are connected to global bit lines GBLm1to m4 respectively. Only the global word line GWLn2 is activated amongthe global word lines GWLn1 to n4, whereby only the local word line LWL2is activated.

[0073] Thus, data of the four memory cells 10 connected to the localword line LWL2 appear on the four global bit lines GBLm1 to m4respectively through the four first selector transistors 11. These fourdata are outwardly read by the read/write amplifier 6 (see FIG. 6)through the global bit lines GBLm1 to GBLm4. At the same time, the fourdata are rewritten (restored) in the four memory cells 10 connected tothe local word line LWL2 through the global bit lines GBLm1 to m4, thefirst selector transistors 11 and the local bit lines LBL1 to 4.

[0074] The transistors 14 (see FIG. 5) enter ON states due to theactivation of the RAASn line, whereby the SRAMs 13 are connected to theglobal bit lines GBLm1 to m4. Therefore, it follows that the data(restored data) rewritten in the four memory cells 10 are held also inthe SRAMs 13.

[0075] Also in the case of writing, write data are held in the fourSRAMs 13 connected to the global bit lines GBLm1 to m4. Therefore, itfollows that finally accessed data are held in the SRAMs 13 in eacharray, whereby it follows that the SRAMs 13 function as cache memories.

[0076] Voltages in respective operation modes are shown in the followingTable 1: TABLE 1 Read from Write in Access Standby FeRAM FeRAM SRAMGWLn2 (selected) ½ Vcc Vcc 0 ½ Vcc LWLn2 (selected) ½ Vcc Vcc 0 ½ VccGWLn1 (non-selected) ½ Vcc ½ Vcc ½ Vcc ½ Vcc LWLn1 (non-selected) ½ Vcc½ Vcc ½ Vcc (floating) ½ Vcc (floating) GBLm1 (selected) ½ Vcc Data DataData LBLm1 (selected) ½ Vcc Data Data Data GBLk1 (non-selected) ½ Vcc ½Vcc ½ Vcc ½ Vcc LBLk1 (non-selected) ½ Vcc ½ Vcc ½ Vcc (floating) ½ Vcc(floating) RAAn (selected) Vcc Vcc Vcc 0 RAAj (non-selected) Vcc 0 0 0CAAm (selected) Vcc Vcc+ Vcc+ Vcc CAAk (non-selected) Vcc 0 0 0 RAASn(selected) 0 0 Vcc+ Vcc+ RAASj (non-selected) 0 0 0 0

[0077] The details of operations of the semiconductor memory deviceaccording to the first embodiment in the respective operation modes arenow described with reference to the above Table 1 and FIGS. 1 to 6.

[0078] Standby Mode

[0079] In this standby (waiting) mode, the semiconductor memory deviceapplies ½Vcc to all global word lines GWL and global bit lines GBL whileapplying Vcc to all RAA 10 lines and CAA lines. Thus, all first selectortransistors 11 and second selector transistors 12 enter ON states,whereby all global word lines GWL and all local word lines LWL areconnected with each other while all global bit lines GBL and all localbit lines LBL are connected with each other. Therefore, all local wordlines LWL and local bit lines LBL reach ½Vcc. In this case, all RAASlines are set to 0 V, whereby all SRAMs 13 enter states separated fromthe global bit lines GBL. Thus, all SRAMs 13 are in states where dataare held. Further, both ends (the local word lines LWL and the local bitlines LBL) of all memory cells 10 of the ferroelectric memory are instates where ½Vcc is applied. Thus, the memory cells 10 are also instates where data are held.

[0080] Read Mode of Ferroelectric Memory

[0081] When the address of the selected array is decided, RAA lines andCAA lines other than those of the selected array reach 0 V. The RAAlines and the CAA lines of the selected array remain in the standbymode, where Vcc is applied. Thus, the local word lines LWL and local bitlines LBL of all non-selected arrays not sharing the RAA lines and theCAA lines with the selected array are separated from the global wordlines GWL and the global bit lines GBL, to enter floating states at½Vcc.

[0082] The global bit lines GBL of the selected array are lowered to 0 Vand thereafter enter floating states. In this case, Vcc is applied tothe RAA lines of the selected array, and hence the first selectortransistors 1 connected to the RAA lines of the selected array areregularly in ON states. Therefore, the global bit lines GBL and thelocal bit lines LBL of the selected array are regularly in connectedstates, whereby the local bit lines LBL of the selected array are alsolowered to 0 V and thereafter enter floating states.

[0083] Then, the CAA lines of the selected array are stepped up from Vccto a voltage Vcc⁺ obtained by adding the threshold voltage of the secondselector transistors 12 to Vcc, in order to prevent a voltage dropcaused by the threshold voltage. The global word line GWLn2 rises toVcc, whereby the local word line LWL2 rises to Vcc through the secondselector transistors 12.

[0084] Therefore, the data of the memory cells 10 connected to the localword line LWL2 appear on the global bit lines GBLm1 to m4 through thelocal bit lines LBL1 to 4 and the first selector transistors 11. Thesedata are read by the read/write amplifier 6 (see FIG. 6).

[0085] Restore (Rewrite) Mode

[0086] The read data defined by the read/write amplifier 6 are returnedto the local bit lines LBL1 to 4 of the selected array by the read/writeamplifier 6 through the global bit lines GBLm1 to m4. In other words,Vcc is applied to the local bit lines LBL for selected cells from whichdata “1” are read while 0 V is applied to the local bit lines LBL forselected cells from which data “0” are read. At this time, the selectedword line LWL2 remains at Vcc, and hence the data “0” are restored(rewritten) in the selected cells from which the data “0” are read.Then, the selected word line falls to 0 V, whereby the data “1” arerestored (rewritten) in the cells from which the data “1” are read.Meanwhile, the RAASn line is made to rise to Vcc⁺, whereby the read dataare written and held also in the SRAMs 13 of the selected array.

[0087] Also as to a write operation, the operation is identical exceptthat the aforementioned restored data are replaced with write data inputfrom an I/O pad.

[0088] SRAM Access Mode

[0089] From the standby state, the semiconductor memory device firstsets all RAA lines to 0 V, thereby separating the global bit lines GBLand the local bit lines LBL from each other. Then, the semiconductormemory device brings all global bit lines GBL into floating states.Thereafter the semiconductor memory device makes the RAASn line risethereby connecting the global bit lines GBL and the SRAMs 13 with eachother for performing access.

[0090] In the semiconductor memory device according to the firstembodiment, as hereinabove described, the ferroelectric memory and theSRAMs 13 are formed on the same p-type semiconductor substrate 31 in astacked manner so that the thickness in the height direction can bereduced, whereby further miniaturization (thinning) can be attained.

[0091] Further, the ferroelectric memory and the SRAMs 13 are formed onthe same p-type semiconductor substrate 31 in a stacked manner so thatno wires having large parasitic capacitances or solder may be employedfor connection of the ferroelectric memory and the SRAMs 13 but theferroelectric memory and the SRAMs 13 can be closely arranged, wherebyhigh-speed data transfer is enabled between the ferroelectric memory andthe SRAMs.

[0092] In the semiconductor memory device according to the firstembodiment, further, the global bit lines GBL are shared by theferroelectric memory and the SRAMs 13, whereby the structure can besimplified as compared with a case of separately providing the globalbit lines GBL respectively.

[0093] In the semiconductor memory device according to the firstembodiment, in addition, the hierarchical structure employing the globalword lines GWL and the global bit lines GBL as well as the local wordlines LWL and the local bit lines LBL is so attained that the wires (thelocal word lines LWL and the local bit lines LBL) connected to thememory cells 10 are shortened, whereby wiring capacitances are reduced.High-speed reading can be performed also according to this.

[0094] In the semiconductor memory device according to the firstembodiment, further, the SRAMs 13 are provided every memory cell arrayand connected to the global bit lines GBL, whereby the SRAMs 13 arrangedevery array can be made to function as high-speed cache memories.

[0095] Further, the ferroelectric memory included in the semiconductormemory device according to the first embodiment requires no high voltagein writing dissimilarly to a flash memory, whereby reduction of voltagesand power consumption can be attained.

[0096] Second Embodiment

[0097] A semiconductor memory device according to this second embodimenthas a structure storing a counter part for counting an access frequencyto memory cells every memory cell array, in addition to theaforementioned structure of the first embodiment.

[0098] More specifically, a NAND circuit 22 and a counter part 23connected to an output of the NAND circuit 22 are provided every memorycell array 21 a, . . . in this second embodiment, as shown in FIG. 13.This counter part 23 is an example of the “frequency detection means” inthe present invention. A CE (chip enable) signal, a signal from a CAAmline and a signal from an RAAn line are input in an input of the NANDcircuit 22. A refresh (REFRESH) signal is output from an output of thecounter part 23. This refresh signal is a signal for performing arewrite operation in the memory cells in response to that the sum ofwrite and read frequencies of memory cells 10 (see FIG. 2) has reached aprescribed count value.

[0099] In other words, this semiconductor memory device according to thesecond embodiment comprises the counter part 23 for detecting the writefrequency and the read frequency of the memory cells 10 and refreshmeans performing rewriting in the memory cells on the basis of that thesum of the write frequency and the read frequency detected by thecounter part 23 has reached the prescribed frequency (256). The controlpart 7 of the first embodiment shown in FIG. 6 is employed as thisrefresh means. The counter part 23 includes an inverter circuit 23 a anda plurality of (eight) TFFs (trigger flip-flops) 23 b, as shown in FIG.14. Each TFF 23 b is constituted of two latch parts consisting of twoinverters and two transfer gates and a transfer gate connecting theselatch parts with each other, although not illustrated.

[0100] The plane layout in the semiconductor memory device according tothe second embodiment and a sectional structure corresponding theretoare now described with reference to FIGS. 15 to 17. In this secondembodiment, a second selector transistor 12 consisting of a pair ofn-type source/drain regions 32 and a gate electrode 33 is formed on thesurface of a p-type semiconductor substrate 31, as shown in FIG. 16.

[0101] Further, the NAND circuit 22 consisting of three n-channeltransistors constituted of four n-type source/drain regions 51 and threegate electrodes 52 is formed on the surface of the p-type semiconductorsubstrate 31. In addition, the counter part 23 including two n-channeltransistors constituted of three n-type source/drain regions 53 and twogate electrodes 54 is formed on the surface of the p-type semiconductorsubstrate 31. The left-end n-type source/drain region 51 constitutingthe NAND circuit 22 is connected to one gate electrode 54 constitutingeither n-channel transistor of the counter part 23. A GND line 41 b isconnected to the intermediate n-type source/drain region 53 of thecounter part 23, while a refresh signal line (REF) 55 is connected tothe left-side n-type source/drain region 53.

[0102] A CAA line 46 is connected to the gate electrode 33 constitutingthe second selector transistor 12. A local word line (LWL) 44 isconnected to one n-type source/drain region 32, while a global word line(GWL) 45 is connected to the other n-type source/drain region 32. Localbit lines (LBL) 42 are formed under the local word line (LWL) 44 throughferroelectric layers 43. The memory cells 10 consisting of ferroelectriccapacitors are constituted of this local word line (LWL) 44, theferroelectric layers 43 and the local bit lines (LBL) 42. Global bitlines (GBL) 47 are formed above the global word line (GWL) 45, tocorrespond to the local bit lines (LBL) 42.

[0103] The plane layout diagram of the counter part 23 is in a layoutshown in FIGS. 15 and 17. The NAND circuit 22 is connected to a CE (chipenable) line 56.

[0104] As hereinabove described, the counter part 23 is positioned underthe memory cells 10 of a ferroelectric memory. In other words, thecounter part 23 and the NAND circuit 22 as well as the memory cells 10of the ferroelectric memory are formed on the same p-type semiconductorsubstrate 31 in a stacked manner.

[0105] Operations of the semiconductor memory device according to thesecond embodiment having the aforementioned structure in respectiveoperation modes are basically similar to those of the aforementionedfirst embodiment. A count-up operation and a refresh (rewrite) operationspecific to this second embodiment are now described.

[0106] As the count-up operation, the semiconductor memory device countsup the counter part 23 one by one every time either a write operation ora read operation is performed on the memory cells 10 of theferroelectric memory in a prescribed memory cell array 21 a (see FIG.13), for example. In this case, rewriting after reading is also includedin the write frequency. When the sum of this read frequency and thewrite frequency reaches a prescribed frequency, the semiconductor memorydevice performs refreshing (rewriting) of the memory cell array 21 a.More specifically, the semiconductor memory device ANDs the CAA line,the RAA line and the CE (chip enable) line every array as an input ofthe NAND circuit 22, thereby outputting a count-up trigger signal fromthe NAND circuit 22.

[0107] If the counter is of 256 bits, for example, the refresh signal(REFRESH signal) is activated when access is made to this memory cellarray 21 a 256 times. Thus, rewriting (refresh operation) is performedon this memory cell array 21 a. This refresh operation is an operationof reading memory cells 10 in the memory cell array 21 a one by one andperforming rewriting.

[0108] In the second embodiment, as hereinabove described, thesemiconductor memory device performs the refresh operation when the sumof the write frequency and the read frequency of the memory cells 10included in the memory cell array 21 a reaches the prescribed value (256times) so that the refresh operation can be periodically performed,whereby it is possible to effectively prevent disturbance, which is sucha phenomenon that data of non-selected cells of the ferroelectric memorydisappear. Thus, a simple matrix ferroelectric memory excellent inimplementation of a high degree of integration and capable of performinghigh-speed writing without requiring a high voltage for writing can beeasily put into practice.

[0109] In the second embodiment, further, the counter part 23 isprovided every memory cell array as hereinabove described so that therefresh operation can be performed every memory cell array, whereby thefrequency of disturbance applied to the memory cells 10 in refreshingcan be reduced as compared with a case of performing the refresh(rewrite) operation on all memory cells. Thus, no data disappearfollowing the refresh (rewrite) operation.

[0110] In the second embodiment, in addition, the counter part 23 andthe ferroelectric memory are formed on the p-type semiconductorsubstrate 31 in a stacked manner so that the thickness in the heightdirection can be reduced, whereby further miniaturization (thinning) canbe attained.

[0111] The embodiments disclosed this time must be considered asillustrative and not restrictive in all points. The scope of the presentinvention is shown not by the above description of the embodiments butby the scope of claim for patent, and all modifications within themeaning and the scope equivalent to the scope of claim for patent arefurther included.

[0112] For example, while each of the aforementioned embodiments hasshown an example of forming a nonvolatile simple matrix ferroelectricmemory and volatile SRAMs (static memories) on the same semiconductorsubstrate in a stacked manner, the present invention is not restrictedto this but another simple matrix memory including bit lines, word linesarranged to intersect with the bit lines and storage means arrangedbetween the bit lines and the word lines or still another nonvolatilememory including memory cells arranged in the form of a matrix may beemployed in place of the ferroelectric memory. For example, a magneticmemory (MRAM: Magnetic Random Access Memory), a phase change memory(OUM: Ovonic Unified Memory) or an anti-fuse (anti-fuse) ROM or the likemay be employed. In addition, nonvolatile memories such as DRAMs otherthan SRAMs may be employed in place of the SRAMs.

[0113] Further, a control circuit or the like may be arranged in placeof either the ferroelectric memory or the SRAMs. For example, a controlcircuit for the ferroelectric memory may be arranged under theferroelectric memory in place of the SRAMs.

[0114] While the SRAMs and the ferroelectric memory share the global bitlines in each of the aforementioned embodiments, the present inventionis not restricted to this but at least either the bit lines or the wordlines may be shared in a case of employing a combination of othermemories.

[0115] While the semiconductor memory device employs the counter as thefrequency detection means detecting the write frequency and the readfrequency of the memory cells of the ferroelectric memory in theaforementioned second embodiment, the present invention is notrestricted to this but frequency detection means other than the countermay be employed.

[0116] While each of the aforementioned first and second embodiments hasshown the example of forming the nonvolatile simple matrix ferroelectricmemory and the volatile SRAMs (static memories) on the samesemiconductor substrate, the present invention is not restricted to thisbut semiconductor substrates 6 and 71 may be pasted to each other afterforming a ferroelectric memory or the like and SRAMs or the like on thedifferent semiconductor substrates 61 and 71 respectively, as shown in amodification of FIG. 18.

[0117] More specifically, memory cells 10 a of the ferroelectric memoryor the like, local word lines LWL and local bit lines LBL or the likeare formed on a surface 61 a of the semiconductor substrate 61, as shownin FIG. 19. Memory cells 13 a of the SRAMs or the like, RAA lines (rowarray selection address lines, CAA lines (column array selection addresslines), RAAS lines, a control circuit (not shown) and the like areformed on a surface 71 a of the semiconductor substrate 71, as shown inFIG. 20. The semiconductor substrate 61 shown in FIG. 19 is pasted ontothe surface 71 a of the semiconductor substrate 71 shown in FIG. 20 in astate directing a back surface 61 b of the semiconductor substrate 61shown in FIG. 19 upward. Thus, the structure shown in FIG. 18 isobtained. Connection between wires on the side of the semiconductorsubstrate 61 and wires on the semiconductor substrate 71 side isperformed with plug electrodes or the like embedded in contact holes(via holes) provided in an interlayer dielectric film arranged betweenboth substrates, for example.

1. A semiconductor memory device comprising: a first memory including abit line, a word line arranged to intersect with said bit line andstorage means (43) arranged between said bit line and said word line;and a second memory (13) different in type from said first memory,wherein said first memory and said second memory are formed on asemiconductor substrate (31, 61, 71).
 2. The semiconductor memoryaccording to claim 1, wherein said first memory and said second memoryare formed on the identical semiconductor substrate (31) in a stackedmanner.
 3. The semiconductor memory device according to claim 1, whereinat least either said word line or said bit line is shared by said firstmemory and said second memory.
 4. The semiconductor memory deviceaccording to claim 1, wherein said first memory includes a plurality ofmemory cell arrays (1 a, 1 b, 1 c, 1 d) each including a plurality ofmemory cells (10), said bit line includes a main bit line (GBL) and anauxiliary bit line (LBL) connected to said main bit line and arrangedevery said memory cell array, said word line includes a main word line(GWL) and an auxiliary word line (LWL) connected to said main word lineand arranged every said memory cell array, and the memory cells (10) ofsaid first memory are connected to said auxiliary word line and saidauxiliary bit line.
 5. The semiconductor memory device according toclaim 4, wherein said first memory includes a ferroelectric memory, andthe memory cells (10) of said ferroelectric memory include saidauxiliary bit line, said auxiliary word line and a ferroelectric layer(43) serving as said storage means arranged between said auxiliary bitline and said auxiliary word line.
 6. The semiconductor memory deviceaccording to claim 5, wherein said second memory includes a staticmemory (13), and said main bit line (GBL) is shared by the ferroelectricmemory constituting said first memory and the static memory constitutingsaid second memory.
 7. The semiconductor memory device according toclaim 4, wherein said main bit line (GBL) and said auxiliary bit line(LB) are formed on said identical semiconductor substrate (31) in astacked manner, and said main word line (GWL) and said auxiliary wordline (LWL) are formed on said identical semiconductor substrate (31) ina stacked manner.
 8. The semiconductor memory device according to claim7, wherein said main bit line (GBL) and said main word line (GWL) areformed above said auxiliary bit line (LBL) and said auxiliary word line(LWL).
 9. The semiconductor memory device according to claim 4, furthercomprising: a first selector transistor (11) connected between saidauxiliary bit line and said main bit line, and a second selectortransistor (12) connected between said auxiliary word line and said mainword line.
 10. The semiconductor memory device according to claim 9,further comprising a first selection line (RAA) connected to the gate ofsaid first selector transistor and a second selection line (CAA)connected to the gate of said second selector transistor.
 11. Thesemiconductor memory device according to claim 4, wherein said secondmemory is connected to said main bit line and provided every said memorycell array.
 12. The semiconductor memory device according to claim 4,further comprising a transistor (14) connected between said secondmemory and said main bit line.
 13. The semiconductor memory deviceaccording to claim 12, further comprising a third selection line (RAAS)connected to the, gate of the transistor connected between said secondmemory and said main bit line.
 14. The semiconductor memory deviceaccording to claim 1, wherein said first memory includes a ferroelectricmemory, said second memory includes a static memory (13), and saidferroelectric memory is formed above said static memory in a stackedmanner.
 15. The semiconductor memory device according to claim 1,wherein said first memory includes a magnetic memory, said second memoryincludes a static memory, and said magnetic memory is formed above saidstatic memory in a stacked manner.
 16. The semiconductor memory deviceaccording to claim 1, wherein said first memory includes a phase changememory, said second memory includes a static memory, and said phasechange memory is formed above said static memory in a stacked manner.17. The semiconductor memory device according to claim 1, wherein saidfirst memory includes an anti-fuse ROM, said second memory includes astatic memory, and said anti-fuse ROM is formed above said static memoryin a stacked manner.
 18. The semiconductor memory according to claim 4,further comprising: frequency detection means (23) arranged every saidmemory cell array for detecting a write frequency and a read frequencyof the memory cells of said first memory included in each said memorycell array, and refresh means (7) performing rewriting with respect tothe memory cells of said first memory included in said memory cell arrayon the basis of that the sum of the write frequency and the readfrequency detected by said frequency detection means has reached aprescribed frequency.
 19. The semiconductor memory device according toclaim 18, wherein said frequency detection means includes a counter(23).
 20. The semiconductor memory device according to claim 18, whereinsaid frequency detection means and said first memory are formed on saidsemiconductor substrate (31) in a stacked manner.
 21. The semiconductormemory device according to claim 1, wherein said second memory (13) isprovided at the rate of one to the plurality of memory cells (10) ofsaid first memory.
 22. A semiconductor memory device comprising: anonvolatile first memory including memory cells arranged in the form ofa matrix; and a volatile second memory (13), wherein said first memoryand said second memory are formed on an identical semiconductorsubstrate (31) in a stacked manner.